1. Field of the Invention
The present invention generally relates to a nonvolatile ferroelectric memory device and a method for manufacturing the same, and more specifically, to a device and a method of improving a structure of a nonvolatile ferroelectric capacitor to minimize an area of a trench capacitor.
2. Description of the Related Art
Generally, a ferroelectric random access memory (hereinafter, referred to as ‘FeRAM’) has attracted considerable attention as a next generation memory device because it has a data processing speed as fast as a Dynamic Random Access Memory (hereinafter, referred to as ‘DRAM’) and preserves data even after the power is turned off.
A FeRAM having a structure similar to a DRAM includes capacitors made of a ferroelectric substance, so that it utilizes the high residual polarization characteristic of the ferroelectric substance in which data is not deleted even after an electric field is eliminated.
A unit cell of a conventional nonvolatile FeRAM device includes a switching element and a nonvolatile ferroelectric capacitor. The switching element performs a switching operation depending on a state of a word line to connect a nonvolatile ferroelectric capacitor to a bit line or disconnect the nonvolatile ferroelectric capacitor from the bit line. The nonvolatile ferroelectric capacitor is connected between a plate line and a terminal of the switching element. Here, the switching element of the conventional FeRAM is an NMOS transistor whose switching operation is controlled by a gate control signal.
Recently, nonvolatile ferroelectric capacitors having three-dimensional structures have been formed with an MOCVD (Metal Organic Chemical Vapor Deposition) process to increase a capacity of memory cell array.
Also, the nonvolatile ferroelectric capacitor having a three-dimensional structure may be formed as a three-dimensional trench capacitor structure using a trench etch structure.
FIG. 1 is a circuit diagram illustrating a cell array block of a conventional nonvolatile ferroelectric memory device.
The cell array block of the conventional nonvolatile ferroelectric memory device includes a top cell array block TCA and a bottom cell array block BCA arranged symmetrically on the sides of a sense amplifier S/A.
Each of the top cell array block TCA and the bottom cell array block BCA includes a plurality of unit cells UC.
Each of the unit cells UC includes a nonvolatile ferroelectric capacitor and a cell transistor T. Nonvolatile ferroelectric capacitor FC is connected between a plate line PL and one terminal of the cell transistor T. Cell transistor T is configured to perform a switching operation in response to a signal on a word line, such as word lines WL0 and WL1, to connect nonvolatile ferroelectric capacitor FC to a bit line BL or /BL or disconnect ferroelectric capacitor FC from bit line BL or /BL.
The cell transistor T has a drain connected to the bit line BL, and a source connected to an electrode, referred to as storage node SN, of the nonvolatile ferroelectric capacitor FC.
The other terminal of the nonvolatile ferroelectric capacitor FC is connected to the plate terminal PL to receive a plate voltage.
The sense amplifier S/A is connected to bit lines BL and /BL.
When the selected word line WL0 of the top cell array block TCA is activated and cell data are transmitted into the bit line BL, the bit line /BL supplies a reference voltage.
On the other hand, when the selected word line WL0 of the bottom cell array block BCA is activated and cell data are transmitted into the bit line /BL, the bit line BL supplies a reference voltage.
The sense amplifier SA senses and amplifies data on the bit lines BL or /BL, and transmits the amplified data into global bit lines GBL and GBLB, or transmits data on the global bit lines GBL and GBLB onto the bit lines BL or /BL.
FIG. 2a is a plan view of cell array block of a conventional nonvolatile ferroelectric memory device.
Referring to FIG. 2a, a plurality of nonvolatile ferroelectric capacitors FC are arranged in rows and columns. Each nonvolatile ferroelectric capacitor FC includes a rectangular storage node SN, a ferroelectric layer FL inside the storage node SN, and a plate line PL inside the ferroelectric layer FL.
FIG. 2b is a cross-sectional diagram view along A-A′ in FIG. 2a. 
Referring to FIG. 2b, cell transistors T are provided below the nonvolatile ferroelectric capacitors FC.
Each cell transistor T includes a drain 2 and a source 4 in a substrate 1, an insulating layer 6, and a gate electrode as the corresponding word line WL sequentially formed over a channel region defined between the drain 2 and the source 4. The drain 2 is connected to the bit line BL, and the source 4 is connected to the nonvolatile ferroelectric capacitor FC through a contact node CN. One trench capacitor FC is formed over one contact node CN.
The nonvolatile ferroelectric capacitor FC includes the storage node SN, the ferroelectric layer FL, and the plate line PL which are sequentially formed. Here, the storage node SN of the nonvolatile ferroelectric capacitor FC is formed to have a ‘U’ shape.
The minimum layout area of the conventional three-dimensional trench capacitor is twice as large as the thickness of the cell node SN and the ferroelectric layer FL and the plate line PL.
The conventional trench capacitor includes a trench in one cell transistor T.
The general cell size is determined depending on the size of the trench. As a result, when the size of the trench is increased or the number of trenches are increased, the area of the capacitor becomes larger so that the size of chip upon which the memory array is provided is also increased.